1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com hv214 features hvcmos ? technolo gy for high performance very low quiescent power dissipation (-10a) low parasitic capacitances dc to 50mhz small signal frequency response -60db typical output off isolation at 5.0mhz cmos logic circuitry for low power excellent noise immunity on-chip shift register, latch and clear logic circuitry flexible high voltage supplies surface mount packages applications medical ultrasound imaging non-destructive evaluation inkjet printer heads optical mems modules ? ? ? ? ? ? ? ? ? ? ? ? ? ? block diagram 250v low charge injection, 8-channel, high voltage analog switch general description the superte x hv214 is a low charge injection, 8-channel, high voltage, analog switch integrated circuit (ic) intended for use in applications requiring high voltage switching controlled by low voltage control signals, such as medical ultrasound imaging, piezoelectric transducer drivers, inkjet printer heads and optical mems modules. input data is shifted into an 8-bit shift register that can then be retained in an 8-bit latch. to reduce any possible clock feedthrough noise, the latch enable bar should be left high until all bits are clocked in. data are clocked in during the rising edge of the clock. using hvcmos ? technology, this device combines high voltage bilateral dmos switches and low power cmos logic to provide ef?cient control of high voltage analog signals. the device is suitable for various combinations of high voltage supplies, e.g., v pp /v nn : +40v/-210v, +125v/-125v, +210v/-40v. sw0 sw1 sw2 sw3 sw4 sw5 sw6 sw7 latches level shifters output switches vdd le cl din clk dout 8-bit shift register d le cl d le cl d le cl d le cl d le cl d le cl d le cl d le cl vnn vpp
2 hv214 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com ordering information device package options 48-lead lqfp 7.00x7.00mm body 1.60mm height (max) 0.50mm pitch 28-lead plcc .453x.453in body .180in height (max) .050in pitch hv214 HV214FG-G hv214pj-g -g indicates the part is rohs compliant (green) absolute maximum ratings parameter value v dd logic power supply voltage -0.5v to +15v v pp - v nn supply voltage 260v v pp positive high voltage supply -0.5v to v nn +250v v nn negative high voltage supply +0.5v to -260v logic input voltages -0.5v to v dd +0.3v analog signal range v nn to v pp peak analog signal current/channel 2.5a storage temperature -65 o c to +150 o c power dissipation: 48-lead lqfp 28-lead plcc 1.0w 1.2w operating conditions sym parameter value v dd logic power supply voltage 4.5v to 13.2v v pp positive high voltage supply 40v to v nn +250v v nn negative high voltage supply -40v to -210v v ih high level input logic voltage v dd -1.5v to v dd v il low-level input logic voltage 0v to 1.5v v sig analog signal voltage peak-to-peak v nn +10v to v pp -10v t a operating free air temperature 0 o c to 70 o c absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. 1 28 4 26 pin con?gurations product marking yy = year sealed ww = week sealed l = lot number c = country of origin* a = assembler id* = green packagin g *may be part of top marking top marking bottom marking yyww hv214pj llllllllll ccccccccccc aaa yy = year sealed ww = week sealed l = lot number c = country of origin* a = assembler id* = green packagin g *may be part of top marking top marking bottom marking yyww hv214fg lllllllll cccccccc aa a 28-lead plcc (pj) 48-lead lqfp (fg) 1 48 28-lead plcc (pj) (top view) 48-lead lqfp (fg) (top view) package may or may not include the following marks: si or package may or may not include the following marks: si or
3 hv214 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com dc electrical characteristics (t a = 25 o c, over recommended operating conditions unless otherwise noted) sym parameter min typ max units conditions r ons small signal switch on-resistance - - 55 i sig = 5.0ma v pp = +40v v nn = -210v - - 49 i sig = 200ma - - 42 i sig = 5.0ma v pp = +125v v nn = -125v - - 36 i sig = 200ma - - 38 i sig = 5.0ma v pp = +210v v nn = -40v - - 32 i sig = 200ma r ons small signal switch on-resistance matching - - 20 % i sig = 5.0ma, v pp = +125v, v nn = -125v r onl large signal switch on-resistance - 23 - v sig = v pp -10v, i sig = 1.0a i sol switch off leakage per switch - - 10 a v sig = v pp -10v & v nn +10v v os dc offset switch off - - 300 mv r load = 100k dc offset switch on - - 500 mv r load = 100k i ppq quiescent v pp supply current - - 50 a all switches off i nnq quiescent v nn supply current - - -50 a all switches off i ppq quiescent v pp supply current - - 50 a all switches on, i sw = 5.0ma i nnq quiescent v nn supply current - - -50 a all switches on, i sw = 5.0ma i sw switch output peak current - - 2.0 a v sig duty cycle 0.1% f sw output switch frequency - - 50 khz duty cycle = 50% i pp average v pp supply current - - 7.0 ma v pp = +40v v nn = -210v all output switches are turning on and off at 50khz with no load - - 5.0 v pp = +125v v nn = -125v - - 5.0 v pp = +210v v nn = -40v i nn average v nn supply current - - -7.0 ma v pp = +40v v nn = -210v all output switches are turning on and off at 50khz with no load - - -5.0 v pp = +125v v nn = -125v - - -5.0 v pp = +210v v nn = -40v i dd average v dd supply current - - 10 ma f clk = 5.0mhz, v dd = 5.0v i ddq quiescent v dd supply current - - 4.0 a --- i sor data out source current 45 - - ma v out = v dd -0.7v i sink data out sink current 45 - - ma v out = 0.7v c in large input capacitance - - 10 pf --- t a ambient temperature range 0 - 70 o c ---
4 hv214 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com ac electrical characteristics (v dd = 5.0v, t a = 25 o c, over recommended operating conditions unless otherwise noted) sym parameter min typ max units conditions t sd set-up time before le rises 150 - - ns --- t wle time width of le 150 - - ns --- t do clock delay time to data out - - 150 ns --- t wcl time width of cl 150 - - ns --- t su set-up time data to clock 15 8.0 - ns --- t h hold time data from clock 35 - - ns --- f clk clock frequency - - 5.0 mhz 50% duty cycle, f data = f clk /2 t r , t f clock rise and fall times - - 50 ns --- t on turn-on time - - 5.0 s v sig = v pp -10v, r load = 10k t off turn-off time - - 5.0 s v sig = v pp -10v, r load = 10k dv/dt maximum v sig slew rate - - 20 v/ns v pp = +40v, v nn = -160v - - 20 v pp = +125v, v nn = -100v - - 20 v pp = +210v, v nn = -40v k o off isolation -30 - - db f = 5.0mhz, 1k//15pf load -58 - - f = 5.0mhz, 50 load k cr switch crosstalk -60 - - db f = 5.0mhz, 50 load i id output switch isolation diode current - - 300 ma 300ns pulse width, 2% duty cycle c sg(off) off capacitance sw to gnd 5.0 12 17 pf 0v, f = 1.0mhz c sg(on) on capacitance sw to gnd 25 38 50 pf 0v, f = 1.0mhz +v spk output voltage spike - - 200 mv v pp = +40v, v nn = -210v, r load = 50 -v spk - - 200 +v spk - - 200 v pp = +125v, v nn = -125v, r load = 50 -v spk - - 200 +v spk - - 200 v pp = +210v, v nn = -40v, r load = 50 -v spk - - 200 power up/down sequence: power up/down sequence is arbitrary except gnd must be powered-up ? rst and powered-down last. v sig must be v nn v sig v pp or ?oating during power up/down transistion. rise and fall times of power supplies v dd , v pp , and v nn should not be less than 1.0msec. 1. 2. 3.
5 hv214 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com logic timing waveforms truth table data in 8-bit shift register le cl output switch state d0 d1 d2 d3 d4 d5 d6 d7 sw0 sw1 sw2 sw3 sw4 sw5 sw6 sw7 l l l off h l l on l l l off h l l on l l l off h l l on l l l off h l l on l l l off h l l on l l l off h l l on l l l off h l l on l l l off h l l on x x x x x x x x h l hold previous state x x x x x x x x x h off off off off off off off off notes : the eight switches operate independently. serial data is clocked in on the lh transition clk. the switches go to a state retaining their present condition at the rising edge of le. when le is low the shift register data ? ows through the latch. d out is high when data in the shift register 7 is high. shift register clocking has no effect on the switch states if le is h. the clear input overrides all other inputs. 1. 2. 3. 4. 5. 6. data in le clock data out off on v out (typ) 50% 50 % 50% 50% t wl e t sd t su t h 50 % 50% t off 50 % t do t on t wc l clr d n+1 d n d n- 1 50% 50% 90 % 10 %
6 hv214 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com test circuits switch off leakage i sol v pp 5v v nn v pp v nn v dd gnd v nn +10v v pp -10v dc of fset on/off v pp 5v v nn v pp v nn v dd gnd v out 100k? t on /t off t est circuit v pp 5v v nn v pp v nn v dd gnd v pp -10v 10k? v out isolation diode current i id v pp 5v v nn v pp v nn v dd gnd v nn v si g crosstalk k cr = 20log v out v in v in = 10 v p- p @5mhz nc 50? v pp 5v v nn v pp v nn v dd gnd 50? output v oltage spike v pp 5v v nn v pp v nn v dd gnd v ou t 1k? 50? +v sp k -v sp k off isolation k o = 20log v out v in v in = 10 v p- p @5mhz v pp 5v v nn v pp v nn v dd gnd v out r load r load r load r load
7 hv214 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com 28-lead plcc (pj) pin description pin function 1 sw3 2 sw3 3 sw2 4 sw2 5 sw1 6 sw1 7 sw0 pin function 8 sw0 9 nc 10 vpp 11 nc 12 vnn 13 gnd 14 vdd pin function 15 nc 16 din 17 clk 18 le 19 cl 20 dout 21 sw7 pin function 22 sw7 23 sw6 24 sw6 25 sw5 26 sw5 27 sw4 28 sw4 pin function 1 sw5 2 nc 3 sw4 4 nc 5 sw4 6 nc 7 nc 8 sw3 9 nc 10 sw3 11 nc 12 sw2 pin function 13 nc 14 sw2 15 nc 16 sw1 17 nc 18 sw1 19 nc 20 sw0 21 nc 22 sw0 23 nc 24 vpp pin function 25 vnn 26 nc 27 nc 28 gnd 29 vdd 30 nc 31 nc 32 nc 33 din 34 clk 35 le 36 clr pin function 37 dout 38 nc 39 sw7 40 nc 41 sw7 42 nc 43 sw6 44 nc 45 sw6 46 nc 47 sw5 48 nc 48-lead lqfp (fg) pin description
8 hv214 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com 48-lead lqfp package outline (fg) 7.00x7.00mm body, 1.60mm height (max), 0.50mm pitch symbol a a1 a2 b d d1 e e1 e l l1 l2 dimension (mm) min 1.40* 0.05 1.35 0.17 8.80* 6.80* 8.80* 6.80* 0.50 bsc 0.45 1.00 ref 0.25 bsc 0 o nom - - 1.40 0.22 9.00 7.00 9.00 7.00 0.60 3.5 o max 1.60 0.15 1.45 0.27 9.20* 7.20* 9.20* 7.20* 0.75 7 o jedec registration ms-026, variation bbc, issue d, jan. 2001. * this dimension is not speci?ed in the jedec drawing. drawings are not to scale. supertex doc. #: dspd-48lqfpfg version, d041309. 1 seating plane gauge plane l l1 l2 vi ew b vi ew b seating plane top view d d1 e e1 b e side view a2 a a1 note 1 (index area d1/4 x e1/4) 48 note: a pin 1 identi?er must be located in the index area indicated. the pin 1 identi?er can be: a molded mark/identi?er; an embedded metal marker; or a printed indicator. 1.
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate product liability indemnification insurance agreement. supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc. website: http//www .supertex.com . ?2009 all rights reserved. unauthorized use or reproduction is prohibited . 1235 bordeaux drive, sunnyvale, ca 94089 te l: 408-222-8888 www .supertex.com 9 hv214 (the package drawing(s) in this data sheet may not re?ect the most current speci?cations. for the latest package outline information go to http://www.supertex.com/packaging.htm l .) doc.# dsfp-hv214 a071009 28-lead plcc package outline (pj) .453x.453in. body, .180in. height (max), .050in. pitch symbol a a1 a2 b b1 d d1 e e1 e dimension (inches) min .165 .090 .062 .013 .026 .485 .450 .485 .450 .050 bsc nom .172 .105 - - - .490 .453 .490 .453 max .180 .120 .083 .021 .032 .495 .456 .495 .456 jedec registration ms-018, variation ab, issue a, june, 1993. drawings not to scale . supertex doc. #: dspd-28plccpj, version a092408. .150 ma x .048/.042 x 45 o 1 .075 ma x 4 26 d d1 e1 e to p v iew vi ew a a a2 a1 seating plane e note 1 (index area) .056/.042 x 45 o base plane .020 min 28 b v iew a b1 horizontal side v iew ve rtical side v iew note 2 .020max (3 places) notes: a pin 1 identi?er must be located in the index area indicated. the pin 1 identi?er can be: a molded mark/identi?er; an embedded metal marker; or a printed indicator. actual shape of this feature may vary. 1. 2.
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